In resent years, along with achieving higher functionality in a logic LSI mounting RAMs and/or CPUs, called system LSI, the number of types and the scale of the RAMs mounted in a chip have been increased. In a RAM unit, wirings and transistors are particularly densely provided on a chip, and they are prone to cause a failure. Thus, yield is generally improved by mounting a spare circuit that is replaceable when a failure occurs, that is, a repair circuit.
Repair circuit design of the system LSI has a problem of increasing test time along with an increase in mounting scale and a problem of increasing the number of external input/output pins for tester connections along with an increase in the number of mounted RAMs, and thus a repair design for reducing the problems has been desired. Therefore, conventionally, BIST (built-in self test) which determines good/bad of the RAM unit by using a circuit mounted inside the chip (Japanese Patent Application Laid-Open Publication No. H08-262116 (Patent Document 1)), and moreover, BISR (built-in self repair) which also determines repair automatically in addition have been developed.
Further, as to a system LSI mounting over hundred kinds of various RAMs in a chip, there are some design methods in consideration of a trade-off of an increase in chip area due to mounting a repair circuit and a yield improvement. Examples are: an I/O group repair method performing I/O repairs per RAM group, wherein the I/O repairs, which have been performed per RAM, are put together into some RAM groups (Japanese Patent Application Laid-Open Publication No. 2006-236551 (Patent Document 2)); and a method of calculating yield for making the number of groups suitable (Japanese Patent Application Laid-Open Publication No. 2007-305670 (Patent Document 3)).